Integrated circuit fabrication may comprise formation of integrated circuitry on and/or within a semiconductor wafer, subsequent singulation of the wafer into a plurality of dice, and finally incorporation of individual die into packages suitable for connecting the die to larger circuits.
The semiconductor wafer may be, for example, a wafer of monocrystalline silicon. The wafer can be considered to have a front side portion, and a back side portion adjacent the front side portion. The integrated circuitry is formed on and/or within the front side portion of the wafer, and subsequently the wafer may be thinned to remove at least some of the back side portion prior to singulation. The thinning may be desired to remove contaminants that may have entered the back side portion during fabrication of circuitry. The thinning may also be desired to reduce the time, expense and difficulty of cutting the wafer during the singulation process, to reduce a die size for packaging constraints, to enhance heat dissipation, etc.
The thinning of the wafer and subsequent singulation of the wafer frequently comprise transfers of the wafer to different devices, and may also comprise flipping of the wafer so that a back side surface is exposed for one device, and a front side surface exposed for a different device. Each transfer of the wafer, and each flip of the wafer, is an additional process step that adds process time and introduces risk of error. Further, multiple consumables may be used during the flipping and transfer. It would be desired to develop new methods for thinning and singulation which reduce wafer transfer and flipping.